The technology of the manufacture of semiconductor devices comprises a great variety of etching processes used for forming trenches and similar structures in multilayer stacks of semiconductor and insulator materials. Integrated circuits are typically comprised of a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein in complex circuits the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies are currently practiced, wherein for complex circuitry based on field effect transistors, such as microprocessors, storage chips, and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency of the resulting devices. During the fabrication of complex integrated circuits using CMOS technology, etching of trenches is commonly performed.
Among other procedural steps heat treatment of semiconductor component at different fabrication states has to be performed in various environments. Annealing processes that alter the microstructure of a (semiconductor) material causing changes in physical properties such as the conductivity, strength and hardness are commonly known. In the manufacture of small-sized transistors annealing may be included in an attempt to provide tensile or compressive strains to channel regions in order to enhance the performance of the transistors. In the context of compliant substances facilitating the employment of strained thin films hetero-epitaxially grown on some seed substrate, etched trenches can be provided for facilitating partial or complete relaxation of the strained thin films.
However, in trenches and similar etched structures, the bottom and side surfaces include portions of material layers of the etched multilayer stack that are exposed to the environment after the etching process was completed. When such etched components are subject to some heat treatment constituents of these material layers can diffuse from the exposed portions out to the environment. The diffusion can severely affect the subsequent manufacturing steps and performance of finished semiconductor devices due to contamination of the annealing environment and the resulting contamination of both already formed layers and structures and those structures being formed during the annealing process.
In the manufacture of InGaNOS devices with relaxed strained InGaN layers, for example, the formation of strained material InGaN islands facilitates the relaxation of the strained layer. The formation of the islands is achieved by etching trenches separating portions of the strained layer. Relaxation is initiated by a heat treatment of the islands that are formed above some compliant layer, e.g., comprising borophosphosilicate glass (BPSG). The heat treatment results in a plastic deformation of the BPSG layer and some reflow thereby elastically relaxing the strained InGaN layer. During the heat treatment, however, boron and phosphorous atoms diffuse out of the portions of the BPSG material that are exposed at the walls and bottoms of the above-mentioned trenches. If the heat treatment is performed in an epitaxial reactor before or during the growth of an active layer, the diffused atoms contaminate the reactor atmosphere and the growing layer and thus affect performance of the built active layer.
It is thus a problem underlying the present invention to provide means to avoid diffusion of material portions of buried layers exposed by etched structures at the inner walls and the bottoms of trenches etched in multilayer stack arrangements.